1. Field of the Invention
The present invention relates generally to the etching of patterns on a semiconductor substrate and more specifically to a method and process to reduce plasma etch fluting during the etching of a pattern on a semiconductor substrate.
2. Description of Related Art
Modem oxide plasma etches based on fluorocarbon feed gases have a tendency to create fluted or scalloped profiles. Fluting is the creation of vertical sidewall irregularities during plasma etching, also referred to as striations, scalloping or sidewall roughness. The problem with the present art is that during etching, the pattern of the modified resist structure that is adjacent to the substrate is directly transferred into the surface of the substrate. The origin of the fluting appears to be a change in the structure of the resist mask during the etch by a combination of either polymer deposition or selective erosion. Fluting creates a number of problems including rough sidewalls, metallized ceramic to metallized ceramic shorts associated with rough tungsten fill and other defects. Fluting dimensions on the order of 20 to 50 nm are particularly problematic as substrate feature dimensions approach the sub 0.2 .mu.m regime.
Fluting is observed in many etches and different resist systems, especially when the etch contains feed gases that tend to form polymer precursors such as CF.sub.4, CHF.sub.3, or C.sub.4 F.sub.8.
In metallized ceramic ("MC") and contact hole processes, it has been found that a carbon rich chemistry (fluorocarbon) is needed for high selectivity of the oxide etch. Polymerizing etch chemistries, such as fluorocarbon etching, produce the worst fluting while non-polymerizing gases like O.sub.2, SF.sub.6, and NF.sub.3, produce the least amount of fluting.
Fluting is also observed with both positive and negative resists. Exposure dose does not appear to affect the extent of fluting, while focus is shown to have an effect.
The thickness of the resist, relative to the thickness of the substrate, has an impact on fluting. The more resist remaining post-etch typically correlates to less fluting. Anti-reflective coatings ("ARC") and mainly ARC open etch and etch chemistries also have an effect on fluting.
Attempts to reduce fluting have included increasing the resist thickness, although, in metallized ceramic, a resist thickness of 7000 to 9000 angstroms did not have an effect for the typical 6500 angstrom etched MC depth. A drawback to increasing the resist thickness is that it will restrict resolution capability as one moves to smaller dimensions on the substrate and will also increase the aspect ratio of resist height to width to greater than 3:1.
Another method to reduce fluting is to optimize etch chemistries, such as by adding O.sub.2. This method reduces fluting but also reduces oxide etch selectivity. The use of SF.sub.6 and NF.sub.3, gases, which are non-polymerizing, can reduce fluting, but they also reduce etch selectivity.
The use of ultraviolet ("UV") light in post development treatment can be used to harden the resist and helps decrease resist erosion by densification of the resist film. This method works better for I-line resists. Chemically amplified films (e.g., DUV resists) tend to shrink upon UV hardening. However, UV hardening, while decreasing resist erosion, has not been shown to reduce fluting.
Other methods of reducing sidewall roughness during dry etching include the choice of dielectric etch chemistry, modification of the initial resist processing and deposition of an SiN sidewall, flood exposure of the initial photoresist mask and optimization of the postbake temperature. Some of the drawbacks of these processes include: added process costs, a reduced process window, are usable only for certain processes or are only marginally effective.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and process to reduce fluting during the etching of a resist pattern on a semiconductor substrate.
It is another object of the present invention to provide a method and process to reduce fluting during the etching of a pattern on a semiconductor substrate that does not restrict resolution capability.
A further object of the invention is to provide a method and process to reduce fluting during the etching of a pattern o n a semiconductor substrate that does not limit oxide etch selectivity.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.